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D*CORE processor and memories

D*CORE processor and memories screenshot


The full D*CORE system with all processor components (control-unit, datapath, PC-logic) on the left, the memory interface (MAR,MDR,MDR) in the center, and the memories (RAM,ROM) on the right. This applet is used in the context of the T3 laboratory course for the interactive exploration of a typical microprocessor system.

As shown here, the hardware of the microprocessor system is complete, but both the microcode and any application programs are missing: these are to be written by you during the step-by-step exercises of our T3/computer-architecture lab course! The idea here is learning-by-doing, but if you prefer to watch a ready-made demo first, just click here to watch the processor running the Sieve-of-Eratosthenes algorithm to calculate and print prime numbers.

First, open the microcode memory editor (popup-menu, edit component) and enter the microcode sequence for the instruction-fetch, arithmetic instructions, load/store instructions, and the jump instructions. (Please read the FAQ document for an explanation about how to enable file access for applets. You might prefer to run Hades as an application via the webstart link instead of as an applet, if you plan to save your microcode).

Click the reset switch to reset the microprogram sequencer, then click the clock switch to generate single clocks for the processor hardware or use the clk-select switch for automatic clocking via the clock-generator. Watch the processor operation.

For details and documentation, check the course material (in German) on our webserver.

Run the applet | Run the editor (via Webstart)

Impressum | 30.11.06