USART 8251 loopback receiver demonstration

Description

This applet demonstrates the receiver part of the USART 8251 chip. To keep the applet as simple as possible, the transmitter of the same 8251 is used as the source for a RS-232 datastream, and a loopback connection is made from the TXD output of the transmitter to the RXD input of the receiver.

As in the previous applets, a stimuli generator component is used to first initialize the USART and to control the data-bus interface during the data transfers. The sequence consists of the following steps:

1. After a reset pulse, a first write operation is used to initialize the 8251 mode register with the value 0xce, which selects asynchronous communication with eight databits, no parity, and two stopbits. It also selects the 16X clock prescaler mode.

2. Next, a value of 0x15 is written to the command register, which enables both the on-chip transmitter and receiver, and also resets the error indicator bits in the status register.

3. A first status register read operation returns the value 0x84. This indicates that the transmitter is ready to accept a data character for transmission (TXRDY or D2=1, also nDSR=0 or D7=1). The receiver has not yet received a character, and its error flags are all cleared.

4. A value of 0x55 is written to the transmit buffer register. As the nCTS input is clear, the transmitter immediately starts transmitting the data, which in turn reaches the receiver via the loopback connection.

5. Note that the RXRDY status output goes high as soon as the receiver detects the first stopbit after the 0x55 data character. This indicates that the receiver has correctly decoded a data character, which should now be read by the host CPU.

6. Another read operation of the status register now returns the value 0x86. The RXRDY bit (D1) is now set, which indicates that a data character is waiting in the receive buffer. All error bits are cleared, indicating a successful transmission.

7. A first read operation of the receive buffer returns the data character 0x55. Note that the read operation also automatically resets the RXRDY output (and the RDRDY bit in the status register. However, the data value itself is not cleared from the receive buffer, and another receive buffer read operation would again return the data value (0x55).

   A short pause is now used, to help identifying the several steps of operations in the waveforms.

8. Next, a value of 0xA7 is written to the transmit buffer register, the transmitter begins transmitting the character, and the value is decoded by the receiver. Once the receiver detects the stopbit, the RXRDY status output is asserted again.

9. We could (and should) perform another read operation now, to access the received data value (0xA7). Instead, we write another character 0x6B to the transmit buffer, which is correctly transmitted and received. Note that RXRDY goes low as soon as the startbit of the new RS-232 transmission is detected, but goes high again once the stopbit has been received.

10. Another data read operation is performed, which returns the value 0x6B - that is, the last received character. The previous received character (here, 0xA7) has been overwritten and lost.

11. A status read operation now returns the value 0x96 which indicates that the transmitter is ready (D2=1) and that a valid character has been received (D1=1). However, the overrun error bit (D4) is also set, which indicates that a previously received data character wasn't read soon enough, and has been overwritten in the meantime.

12. To reset the overrun error bit in the status register, a command write operation with the ER bit set is now performed.

You can also click the "run" button in the simulator control panel to continue the simulation and try to transmit and receive more characters. The following screenshot shows example waveforms for the above sequence. Note the behaviour of the RXRDY signal, and the overrun-error flag being set in the status register afterwards.

The next applet demonstrates the receiver error handling, with deliberate parity and frame errors.

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