The 'dcf_in' signal is expected to be low (0) during the short (0.1 second) and long (0.2 second) pulses of the DCF-77 clock signal, and high in the intervals between. This requires a corresponding radio receiver that converts the analog radio signal into this digital representation.
When no 'dcf_in' impulse is detected for more than two seconds (missing input signal), the wait-counter subdesign asserts its 'timeout' output, connected to the 'wait_37+' input of the state machine. The state machine then enters the invalid state and waits until new pulses arrive.
Depending on the duration of a 'dcf_in' pulse, the state-machine will transition to its 'short' or 'long' states. Also, as soon as a 'dcf_in' impulse arrives, the 'reset_wait' input is asserted to reset the wait counter. If the wait counter output is 'wait_14_to_16' at the next 'dcf_in' impulse, a one-second pulse interval is detected, and the corresponding bit (short/low) is clocked into the 59-bit shift register.
If a two-second delay between pulses is detected, the next pulse marks the beginning of a new minute. The state-machine now asserts its 'load clock' output that instructs the output registers of the DCF-77 clock to load their input from the current 59-bit shift-register contents.
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