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Multiplexed seven-segment display (4 digits)

Multiplexed seven-segment display (4 digits) screenshot


A 4-digit multiplexed seven-segment display. While it is possible to drive each individual segment of a seven-segment (or 20-segment or dot-matrix) display with its own driver circuit, the number of driver transistors and wires becomes impractical when more than a few displays are involved. It is much more common to use a multiplexed display architecture, as demonstrated in this applet.

The data to be displayed is stored in the 16x4 bit SRAM chip (74219) at memory locations 0..3 (one 4-bit word for each of the 4 display digits). The two least-significant output bits 0..1 (A,B) of the free-running 74590 counter chip are connected to both the address inputs A0 and A1 of the RAM chip and the select inputs of the 74138 3:8 demultiplexer. The data from the addressed memory location is used to drive the 7449 seven-segment decoder chip, which in turn drives the A..F segment-lines connected to all seven-segment display components. The decimal-point LED is not used in the applet and tied to GND. At any time, only the demultiplexer output corresponding to the current address is active (low), which in turn enables the LED segments driven by the 7449 decoder.

Note that the multiplexing trick only works, because each LED (light-emitting diode) functions as a diode electrically. For other display technologies (like standard light-bulbs), extra diodes must be used in series with each display component, in order to avoid short-circuits. Also note that the logic to write the data into the RAM chip in the first place has been omitted from the applet.

Obviously, only 7 segment-lines and 4 digit-lines are required for the four-digit display, for a total of 11 connections (or 12 if the decimal-point segment is used, too). Even in this small example, the individual connection of each seven-segment display would require 28 (7*4) or even 32 (8*4 including decimal-point) connections.

On the other hand, each display is only activated during 1/4th of the total display cycle. To avoid flicker, each digit is refreshed at a rate of at least 200 Hz in practice.

The next applet shows what happens when the number of digits in a multiplexed display gets larger.

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Impressum | 24.11.06