The data to be displayed is stored in the 16x4 bit SRAM chip (74219) at memory locations 0..7. The output bits 0..2 (A,B,C) of the free-running 74590 counter chip are connected to both the address inputs 0..2 of the RAM chip and the data inputs of the 74138 3:8 demultiplexer. The data from the addressed memory location is used to drive the 7449 seven-segment decoder chip, which in turn drives the A..F segment-lines connected to all seven-segment display components. The decimal-point LED is not used in the applet and tied to GND. At any time, only the demultiplexer output corresponding to the current address is active (low), which in turn enables the LED segments driven by the 7449 decoder. The logic to write the data into the RAM chip in the first place has been omitted from the applet.
Obviously, only 7 segment-lines and 8 digit-lines are required for the 8-bit display, for a total of 15 connections (or 16 if the decimal-point segment is used, too.) Note that the individual connection of each seven-segment display would require 56 (7*8) or even 64 (8*8 including decimal-point) connections.
On the other hand, each display is only activated during 1/8th of the total display cycle. In the actual circuit, this in turn results in a dim display. While it is possible to increase the brightness somewhat via increased currents (including operating the LEDs beyond their maximum currents and voltages), the degree of multiplexing usually is limited to about eight (or so) digits.
Unfortunately, the typical refresh rates used for multiplexed displays of at least 200 Hz are impractical for a simulation. Typical monitor refresh rates are between 60 and 100 Hz, but repaint rates in Hades are limited to about 20 redraws per second in practice. Therefore, only one (or a few) LEDs are activated during each refresh, and the display is hard to read.
The next applet demonstrates a trick to restore user-friendly behaviour for heavily multiplexed display, based on the use of special "smart" display components.
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