TAMS / Java / Hades / applets (print version): contents | previous | nextEdge-triggered D-type flipflop
DescriptionThis example presents a positive-edge triggered D-flipflop.
The basic structure obviously consists of two basic D-type latches
which are connected in series and controlled by inverted phases
of the clock signal.
The following image shows example-waveforms for several
signals inside the D-flipflop.
Run the applet | Run the editor (via Webstart)
Impressum | 24.11.06
http://tams.informatik.uni-hamburg.de/applets/hades/webdemos/16-flipflops/20-dlatch/dff_print.html