LFSR-based signature analysis register (8-bit)

Description

This applet demonstrates a so-called signature analysis register. The circuit is based on the standard linear feedback shift register (see the previous applet), but with extra XOR-gates between the flipflops. Each such XOR-gate provides one data input to the signature analysis register.

The choice where to add such extra inputs to the basic linear-feedback shift register is completely arbitrary, and up two n extra inputs can be used to an n-stage LFSR. In the applet, only the first and fourth stage of the linear-feedback shift-register are modified to include those extra XOR gates, for a total of two data inputs. This should make it easy to recognize the basic LFSR structure. Simply click the input switches, or type the 'a' and 's' bindkeys to control the data inputs during the simulation.

At each active edge of the clock signal, the next state of the LFSR depends on both its current state and the current values of the extra data inputs. When all data inputs are low, the LFSR simply follows the standard feedback sequence(s) as defined by the structure of the XOR gates in its feedback path. However, whenever the external data inputs are high during the active edge of the clock signal, the flipflop driven by the corresponding XOR gate will be toggled with respect to the default feedback sequence, and therefore modify the feedback sequence.

Obviously, the value of the signature analysis register depends on both the initial state (after a reset), and all data input values clocked into the register since the initialization. The final register contents after m clock pulses can be interpreted as a signature of all data inputs during those clock cycles. Naturally, different input value sequences can result in the same final signatures, because a register with n stages has only 2ⁿ different states, but the probability of such aliasing falls exponentially with increasing number of stages. For example, the probability of accidental aliasing is only 2^-32 in a 32-stage register.

Signature analysis registers are often used in combination with standard LFSRs for on-chip selftest of VLSI circuits. The idea, explained in more detail in the following applet, is to use a first standard LFSR to generate a long sequence of pseudo-random input data for a block of logic. The outputs of the block of logic are connected to the data inputs of a second signature analysis register. After running both registers for a predefined number of clock cycles, the result value of the signature analysis register is read-out and compared with the constant 'golden' signature value calculated beforehand for the intact circuit. If the signatures differ, the block of logic is known to be defect, while matching signatures indicate that the block of logic is working (with a very high-probability). Two major advantages of using LFSRs for the pattern generation and signature analysis are their low cost and high operating frequency.

A variant of the signature analysis register, the so-called BILBO, can be used in different operating modes as each of a standard D-type register, standard shift-register, LFSR-based pattern generator, and LFSR-based signature analysis register.

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