The two-input NOR2 gate shown on the left is built from four transistors. The parallel connection of the two n-channel transistors between GND and the gate-output ensures that the gate-output is driven low (logical 0) when either gate input A or B is high (logical 1). The complementary series-connection of the two transistors between VCC and gate-output means that the gate-output is driven high (logical 1) when both gate inputs are low (logical 0). The net result is the logical NOR function:
NOR2 OR2 A B | Y A B | Z --------+----- ------+---- 0 0 | 1 0 0 | 0 0 1 | 0 0 1 | 1 1 0 | 0 1 0 | 1 1 1 | 0 1 1 | 1
As shown on the right, the corresponding OR gate is constructed from the NOR2 followed by a standard static inverter.
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