Index of /publications/2003/dissMaeder/benchmark/opw/oldVerilog

 Name                                         Last modified      Size  
 Parent Directory                                                  -   
 vcs62.time                                   2002-07-27 09:37  5.2K  
 vcs62.out                                    2002-07-27 09:24   92   
 vcs62.csh                                    2002-07-27 09:19  909   
 opwVcs.v                                     2002-07-27 09:09  2.7K  
 vcs62.time-1                                 2002-07-27 08:59  2.8K  
 verilog.log                                  2002-07-12 15:15   67   
 vcs61.time                                   2002-03-07 16:01  2.8K  
 verilog.time                                 2001-12-20 11:30  405   
 vcs60.time                                   2001-12-20 11:29  1.0K  
 vcs601.time                                  2001-12-20 11:29  2.1K  
 work/                                        2001-12-16 13:51    -   
 vcs.csh                                      2001-11-05 10:03  726   
 vcs.out                                      2001-10-12 17:26   63   
 ncsim.time                                   2001-10-12 13:26  1.1K  
 ncsim.out                                    2001-10-12 13:23  188   
 cds.lib                                      2001-10-12 13:22   92   
 ncsim.scr                                    2001-10-12 13:21    9   
 verilog.out                                  2001-10-12 12:04   67   
 verilog.csh                                  2001-10-12 12:00  492   
 make-veri                                    2001-10-12 11:56  309   
 ncsim.csh                                    2001-10-12 11:51  1.3K  
 hdl.var                                      2001-10-12 11:46   64   
 make-vlog                                    2001-10-12 11:45  525   
 opwTst.v                                     2001-10-12 11:43  2.7K  
 opwS.v                                       2001-10-05 12:58   73K