Sun Ultra-60 SunOS 5.8 2*360MHz 1280MB AMD K6 III Windows ME 400MHz 160MB Synopsys vhdlan 2000.12 2001.09 / 2001.10 vhdlsim 2000.12 2001.09 cylab 2000.12 2001.09 cysim 2000.12 2001.09 scsim 2000.12 2001.10 vcs 6.0.1 Compiler version 6.0 vcs script version 4.1.1.patch2 VirSim Unterschiede in den Versionen: vhdlsim/cysim -keine signifikanten Unterschiede, s. opw scirocco -neues Konzept, explizite Trennung compiler, simulation -l"auft auch f"ur synthetisierte Netzliste! ? Fehler bei compiled sim opw ? mixed-mode Cadence cv 2.84-p001 ev 2.84-p001 sv 2.84-p001 (_vlog _novlog) ncvhdl 3.11.(p1) ncvlog 3.11.(p1) ncelab 3.11.(p1) ncsim 3.11.(p1) verilog 3.11.p001 VERILOG-XL ModelSim vcom 5.3d vsim 5.3d VHDL Simili vhdlp 1.5b17 vhdle 1.5b17 Beispiele: aus simili.time cylab -info 1 scs -perf_data -partition ... ncelab -v93 -messages ev -v93 -messages bei Netzlisten: #Instanzen und #Netze aus Synthese... Die Ausgabe f"ur die VHDL Hierarchie ist vom Simulator und dessen Implementation der Gatter-/VITAL-Bibliothek abh"angig (s. Ausgaben von ev und ncelab). Auch bei gemischten Simulationen VHDL-/Verilog- ergeben sich Abweichungen. ----------------------------------------------------------------------------- instances processes signals ports tlcTst 1 1 5 - tlcWalk(behave) - 4 4 3i 2o tlcWalk(behave1) - 1 - 3i 2o ncelab... components processes signals /bit walkCfg 2 5 9 /12 tlcWalk(behave) 2 4 4 walk1Cfg 2 2 5 / 8 tlcWalk(behave1) 2 1 - ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- instances processes signals ports opwTst 1 1 10 - opw 1 6 12 9i 1io alu - 1 - 3i 1o ncelab... components processes signals /bit tstCfg 3 8 22 /272 opw 3 7 12 alu 2 1 - ----------------------------------------------------------------------------- AMS-Prozess cells nets ports opw 544 607 32 alu 201+33 252+82 52+51 ncelab... components processes signals /bit tstCfg 780 3489 3610 /3632 opw 780(544) 3488(2602) 3600(2714) alu 236 886 886 ----------------------------------------------------------------------------- UMC-Prozess cells nets ports opw 595 594 32 alu 193+34 244+83 52+51 ncelab... components processes signals /bit tstCfg 824 3202 3179 /3201 opw 824(595) 3201(2320) 3169(2288) alu 229 881 881 ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- instances processes signals ports tstClock 2 3 25 - dcfClock 7 - 53 11i 7o alaBlk - 6 24 19i 7o alaFsm - 3 4 8i 6o clkGen - 7 3 3i 4o ctrlFsm - 4 6 10i 8o dcfFsm - 7 13 3i 14o display - 2 - 27i 5o timBlk - 2 1 22i 16o dcfSend - 2 1 7i 1o clockPkg, compPkg, simEnvPkg ncelab... components processes signals /bit cfgClock 10 48 130 /405 alaBlk 2 6 24 alaFsm 2 3 4 clkGen 2 7 3 ctrlFsm 2 4 6 dcfFsm 2 19 13 display 2 2 - timBlk 2 2 1 dcfSend 2 2 1 ----------------------------------------------------------------------------- AMS-Prozess cells nets ports dcfClock 7 158 33 alaBlk 510 598 56 alaFsm 85 98 15 clkGen 46+10+10 73+28+28 7+20+20 ctrlFsm 175 195 21 dcfFsm 148+26+6+10+6 184+41+16+28+16 41+24+12+20+11 display 397 473 93 timBlk 182 257 93 ncelab... components processes signals /bit cfgClock 1621 6472 6811 /6876 dcfClock 1620 6467 6785 alaBlk 512 2187 2248 alaFsm 87 305 305 clkGen 68 243 277 ctrlFsm 177 639 642 dcfFsm 198 865 950 display 399 1419 1406 timBlk 184 808 831 dcfSend 2 2 1 ----------------------------------------------------------------------------- UMC-Prozess cells nets ports dcfClock 11 162 33 alaBlk 571 619 56 alaFsm 94 103 15 clkGen 40+10+10 63+28+28 7+20+20 ctrlFsm 201 212 21 dcfFsm 167+18+6+10+6 188+33+16+28+16 41+24+12+20+11 display 358 431 93 timBlk 222 280 93 ncelab... components processes signals /bit cfgClock 1727 6388 6502 /6560 dcfClock 1726 6383 6476 alaBlk 573 2168 2161 alaFsm 96 323 319 clkGen 62 245 261 ctrlFsm 203 691 685 dcfFsm 209 740 746 display 360 1343 1326 timBlk 224 864 844 dcfSend 2 2 1 ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- instances processes signals ports mulTst 1 1 3 - mul8 - 13 12 2i 1o mul16 - 25 24 2i 1o mul24 - 37 36 2i 1o mul32 - 49 48 2i 1o mulPkg ncelab... components processes signals /bit mul8Cfg 8 2 14 15 /216 mul8Cfg 16 2 14 15 /328 mul8Cfg 24 2 14 15 /440 mul8Cfg 32 2 14 15 /552 mul8 .. 2 13 12 mul16Cfg 16 2 26 27 /816 mul16Cfg 24 2 26 27 /1024 mul16Cfg 32 2 26 27 /1232 mul16 .. 2 25 24 mul24Cfg 24 2 38 39 /1800 mul24Cfg 32 2 38 39 /2104 mul24 .. 2 37 36 mul32Cfg 32 2 50 51 /3168 mul32 .. 2 49 48 ----------------------------------------------------------------------------- AMS-Prozess cells nets ports mul8x8 431+171 462+200 32+50 mul8x16 738+300 785+345 48+74 mul8x24 1083+433 1146+494 64+98 mul8x32 1280+549 1359+626 80+122 mul16x16 1788+477 1851+537 64+98 mul16x24 2515+593 2594+669 80+122 mul16x32 3212+823 3307+915 96+146 mul24x24 3931+775 4026+866 96+146 mul24x32 4802+811 4913+918 112+170 mul32x32 6473+885 6600+1007 128+194 ncelab... components processes signals /bit mul8Cfg 8 604 1760 1762 /1806 mul8x8 604 1759 1759 mul8Cfg 16 1040 3015 3017 /3085 mul8x16 1040 3014 3014 mul8Cfg 24 1518 4433 4435 /4527 mul8x24 1518 4432 4432 mul8Cfg 32 1831 5429 5431 /5547 mul8x32 1831 5428 5428 mul16Cfg 16 2267 6636 6638 /6730 mul16x16 2267 6635 6635 mul16Cfg 24 3110 9188 9190 /9306 mul16x24 3110 9187 9187 mul16Cfg 32 4037 11971 11973 /12113 mul16x32 4037 11970 11970 mul24Cfg 24 4708 14048 14050 /14190 mul24x24 4708 14047 14047 mul24Cfg 32 5615 17003 17005 /17169 mul24x32 5615 17002 17002 mul32Cfg 32 7360 22271 22273 /22461 mul32x32 7360 22270 22270 -----------------------------------------------------------------------------