Setting a new performance
standard in public key cryptography
The eFast™ exponentiator sets a new performance standard for public
key cryptography. The patent pending eFast™ technology shrinks the
gate count that is required for implementing fast exponentiations on an
ASIC or a FPGA. If you are implementing cryptographic accelerators for
virtual private networks or other crypto accelerators the eFast™
technology will speed up your product or shrink the required space required
for exponentiations.
For micro controllers
for smart cards the technology will give the manufacturer of the micro
controller a huge cost advantage.
Half the size
For a normal
ASIC the cost of increasing the chip area is calculated by raising it
to the power of four. A preliminary test result shows that the eFast™
technology can half the size of the numerical processing unit (NPU) that
is required to implement a given performance on a ASIC. On an FPGA implementation
the speed increase in comparison with known methods for exponentiation
is spectacular.
The eFast™
Product
eFast™ Exponentiator prototype PCI card with FPGA
Demo software for the card
Drivers for Linux and Windows 2000
(Shipping 3ed quarter 2001)
(Shipping 3ed quarter
2001)
eFast™ IP-cores for ASIC and for FPGA
(Shipping 3ed quarter
2001)
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and new about eFast™ Technology
Send a mail to info@protego.se with
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Legal
notes:
All
above specifications are based on development data and should be considered
preliminary and could be changed without notice.
eFast™
and other technology described in this document is covered by Patents
and pending Patents worldwide and brand names owned by Protego Information
AB™ and by Novacatus Invest AB™.
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