rm -rf WORK/*
echo vhdlan
echo "vhdlan -nc -cycle -event opwYTst.vhd"			>> sci.time
echo "------------------------------------------------"		>> sci.time
(time vhdlan -nc -cycle -event opwYTst.vhd)			>>& sci.time
echo ""								>> sci.time

set umcDir = "/local/tech1.1/umc/UMCL18U250D2_2.2/verilog_simulation_models"
set outCnt = 1
foreach vlopt ("+cli" "" "+rad+2" "+nospecify +notimingcheck" \
	"+cli +nospecify +notimingcheck" "+rad+2 +nospecify +notimingcheck")
  echo scsim -verilogcomp \"-y \$umcDir +libext+.v $vlopt \\	>> sci.time
  echo "      " \$umcDir/UDPS.v timescale.v opwS.v\" \\		>> sci.time
  echo "      " -nc -time ps -include sci.scr -output tmpout \\	>> sci.time
  echo "      " -event_all -generics_file sci.gen		>> sci.time
  echo "------------------------------------------------"	>> sci.time
  echo -n  scsim: $vlopt
  foreach run (1 2 3)
    echo -n " "$run
    (time scsim -verilogcomp "-y ${umcDir} +libext+.v $vlopt ${umcDir}/UDPS.v timescale.v opwS.v" -nc -time ps -include sci.scr -output tmpout -event_all -generics_file sci.gen tstYCfg) >>& sci.time
    mv tmpout tmpout.$outCnt
    @ outCnt++
  end
  echo ""
  echo "" >> sci.time
  rm -rf csrc* simv*
end
unset umcDir
unset outCnt
