rm -rf WORK/*
echo vhdlan
echo "vhdlan -nc -cycle -event <vhd-File>"			>> sci.time
echo "------------------------------------------------"		>> sci.time
(time vhdlan -nc -cycle -event compPkgV.vhd \
	simEnvPkg.vhd dcfSend.vhd tstClockV.vhd)		>>& sci.time
echo ""								>> sci.time

set amsDir = "/local/tech1.1/ams/v3.30/artist/HK_0.35/veritools"
set outCnt = 1
foreach vlopt ("+cli" "" "+rad+2" "+nospecify +notimingcheck" \
	"+cli +nospecify +notimingcheck" "+rad+2 +nospecify +notimingcheck")
  echo scsim -verilogcomp \"-v \$amsDir/HRDLIB.v -v \$amsDir/udp.v \\	\
								>> sci.time
  echo "      " $vlopt timescale.v dcfClockS.v\" \\		>> sci.time
  echo "      " -nc -time ps -include sci.scr -output tmpout \\	>> sci.time
  echo "      " -event_all cfgClock				>> sci.time
  echo "------------------------------------------------"	>> sci.time
  echo -n  scsim: $vlopt
  foreach run (1 2)
    echo -n " "$run
    (time scsim -verilogcomp "-v ${amsDir}/HRDLIB.v -v ${amsDir}/udp.v $vlopt timescale.v dcfClockS.v" -nc -time ps -include sci.scr -output tmpout -event_all cfgClock) >>& sci.time
    mv tmpout tmpout.$outCnt
    @ outCnt++
  end
  echo ""
  echo "" >> sci.time
  rm -rf csrc* simv*
end
unset amsDir
unset outCnt
