set outCnt = 1
source make-veri

foreach xlopt ("-q" "-q +notimingchecks +turbo+3 +twin_turbo")
  echo verilog tstClock.v dcfClockS.v -v umc18co.v -l tmpout \\	>> verilog.time
  echo "       " $xlopt						>> verilog.time
  echo "------------------------------------------------"	>> verilog.time
  echo -n running verilog
  foreach run (1 2)
    echo -n " "$run
    (time verilog tstClock.v dcfClockS.v -v umc18co.v -l tmpout $xlopt)	\
								>>&verilog.time
    mv tmpout tmpout.$outCnt
    @ outCnt++
  end
  echo ""							>> verilog.time
  echo ""
end
unset outCnt
