README.txt	ajm						15-dec-2022
-memorySim.tgz	simple simulation models: ROM and RAM
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memPkg.vhd	-package: component declarations + fileIO-Type
rom.vhd		-ROM
ramB.vhd	-RAM, bidirectional data-bus (tristate)
ramIO.vhd	-RAM, separate input- + output-bus
		 compatible with Intel-FPGAs
procTest.vhd	-sample design (processor + instruction- and data-memory)
instMem-16bitSample.dat	-sample data for instr. memory

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README.txt - end
