-- tstClock3.vhd	ajm					06-jun-2017
--
-- entity	tstClock3
--			-top-level testbench, entity:	clock
-- architecture	stimuli
--			-the stimuli generation is for the sample push-button
--			 interface: set_time/set_ala + set_mins/set_hrs
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity tstClock3 is
generic (	tClk	: time		:= 1 us);	-- 1 MHz
end entity tstClock3;

------------------------------------------------------------------------------
architecture stimuli of tstClock3 is
  -- component decl.	------------------------------------------------------
  ----------------------------------------------------------------------------
  component clock is
  port(	reset		: in  std_logic;	-- async. reset		L
	clk1us		: in  std_logic;	-- 1 MHz clock		R
--	dcfsig		: in  std_logic;	-- DCF77 signal
	set_time	: in  std_logic;	-- Set-Time   button	H
	set_alarm	: in  std_logic;	-- Set-Alarm  button	H
	set_mins	: in  std_logic;	-- Set-Min    button	H
	set_hrs		: in  std_logic;	-- Set-Hour   button	H
	alarm_tog	: in  std_logic;	-- alarm      button	H
--	disp_date	: in  std_logic;	-- date       button	H
--	disp_wday	: in  std_logic;	-- weekday    button	H
	seldgt		: out std_logic_vector (5 downto 0);	--digit lines	
	decoded		: out std_logic_vector (6 downto 0);	--7 Seg output
	alarm_act	: out std_logic;	-- alarm LED on		H
	alarm_out	: out std_logic);	-- alarm ringer		H
--	dcfsok		: out std_logic);	-- signal quality	H
  end component clock;

  -- signal decl.	------------------------------------------------------
  ----------------------------------------------------------------------------
  signal reset		: std_logic := '0';
  signal clk1us		: std_logic := '0';
--  signal dcfSig		: std_logic;
  signal butTime	: std_logic := '0';
  signal butAla		: std_logic := '0';
  signal butMins	: std_logic := '0';
  signal butHrs		: std_logic := '0';
  signal butAlarm	: std_logic := '0';
--  signal butDate	: std_logic := '0';
--  signal butWDay	: std_logic := '0';
  signal seldgt		: std_logic_vector (5 downto 0);
  signal decoded	: std_logic_vector (6 downto 0);
  signal alarmLed	: std_logic;
  signal alarmRing	: std_logic;
--  signal dcfsok		: std_logic;


begin
  -- instances		------------------------------------------------------
  ----------------------------------------------------------------------------
  clockI: clock
    port map	(reset, clk1us,
		 butTime, butAla, butMins, butHrs, butAlarm,
		 seldgt, decoded, alarmLed, alarmRing);

  -- processes		------------------------------------------------------
  ----------------------------------------------------------------------------

  -- clock, period: tClk 			------------------------------
  clkP: process
  begin
	clk1us <= '0';	wait for tClk/2;	-- 0.5 us
	clk1us <= '1';	wait for tClk/2;	-- 0.5 us
  end process clkP;
 
  -- reset, trigger				------------------------------
  rstP: process
  begin
	reset <= '1';	wait for tClk/10;	-- 0.1 us
	reset <= '0';	wait for tClk/5;	-- 0.2 us
	reset <= '1';	wait for tClk/2;	-- 0.5 us
	wait on reset;
  end process rstP;

  -- stimuli generator				------------------------------
  stiP: process
    -- local (overloaded) procedures		------------------------------
    procedure pushBut(	pushT, runT		: in time;
			signal but		: out std_logic) is
    begin
      but <= '1';	wait for pushT;
      but <= '0';	wait for runT-pushT;
    end procedure pushBut;			-- one button

    procedure pushBut(	pushT, runT		: in time;
			signal but1, but2	: out std_logic) is
    begin
      but1 <= '1';
      but2 <= '1';	wait for pushT;
      but1 <= '0';
      but2 <= '0';	wait for runT-pushT;
    end procedure pushBut;			-- two buttons
  begin
    ---------------------------------------------- <action>    <time-Sum>
    wait for 1 sec;				--		 1

    -- set alarm: 	10:34
    pushBut( 5 sec,  6 sec, butAla, butHrs);	-- hour   +10	 7
    pushBut(17 sec, 18 sec, butAla, butMins);	-- minute +34	25

    -- activate alarm
    pushBut(300 ms, 1 sec, butAlarm);		-- alarm on	26

    -- set time: 	10:33
    pushBut( 5 sec,  6 sec, butTime, butHrs);	-- hour   +10	32
    pushBut(16300 ms, 17 sec, butTime, butMins);-- minute +33	49

    -- run for 61 sec. => alarm after 60 sec	--
    wait for 61 sec;				--		(110) -> 10:34

    -- stop alarm
    pushBut(300 ms, 1 sec, butAlarm);		-- alarm off	(111) -> 10:34

    wait;
  end process stiP;

end architecture stimuli;