In order to minimize a given logic function in a two-level and-or representation, one has to merge minterms into other terms, which cover multiple (2,4,8,16, etc) minterms each. Such terms are much cheaper in the resulting logic realization.

The basic idea of a KV diagram is to represent a given boolean function in a two-dimensional function table with a special arrengement of terms. In a KV diagram, neighbored entries represent function-table entries which differ in only one variable. Therefore, drawing 'loops' around multiple minterms is equivalent to find merges of minterms. For an example, click here.

The applet visualizes this process, because at each step the two-level logic realization of the function is plotted in a seperate window and updated whenever you combine terms. You can watch how the function schematic gets simpler (and the logic realization gets cheaper) while you minimze the function.

• functions with up to 6 inputs and up to 8 outputs
• minimization in disjunctive (DNF, and-or) and conjunctive (KNF, or-and) forms
• minimization of multi-output functions (DNF only)
• several example functions
• user-defined functions
• student mode for visualization
• circuit schematics display