The processing of binary information takes place in digital computers with help of logical circuits.
A network has n inputs and m outputs:
At the inputs, binary values x1,x2,..., xn with xi out of {0,1}can be input. At the outputs, binary words are output according to the input-signals y1,y2,..., ym with yi out of {0,1}.
Is the output only refering to its momentarily input, so it is named control-network. Is it also refering to former outputs (repatriation of the outputs), so it is called a control-mechanism. Information can be stored by means of the repatriation.
As direct repatriations are rarely easy to handle even with small control mechanisms (Hazards), a clock-device is inserted into the repatriation. For a better overview, the switch-network is divided into two parts: the first part is used for the regulation of the consequence-state (delta-switch-network), the second calculates the edition-values (Lambda-Schaltnetz).
The control-mechanism is designed as follows:
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Delta-switch-network: | here, out of the state, in which the machine is now, and the input-condition the following state is calculated. |
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Bar-limb: | here, the condition in which the machine is now is stored by Flip-Flops. With a clock-signal, the following condition, that has been computed by the delta-network, becomes the new condition in the delta- and lambda-network. A condition-alteration can only take place with a clock-signal. |
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Lambda-network: | the current outputs are calculated here. With a Moore-machine, these refer only to the current condition. However with a Mealy-machine, also the inputs are included to the calculations. So, also between two clock-signals alterations can be generated. Mealy-machines are not mightier however, because (apart from a delay) there is always an equivalent Moore-machine. |
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An important description-method for control mechanisms are Finite State Machines. JavaFSM uses these for the design and offers the possibility, to export defined machines as control mechanisms to VHDL and KISS.