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Femtojava processor structure (multicycle)

Femtojava processor structure (multicycle) screenshot


This applet demonstrates the Femtojava Processor. It shows a Multicycle Implementation of the FemtoJava Microcontroller [3] at RT-level. The design has 35 component instances and 95 connections. This design is compatible with the VHDL version [2], and a structural VHDL can be generated. The student can run a step-by-step simulation, in order to understand the microcode operations. A script can start and stop the simulation in a specific break-point. Moreover, we have implemented some power estimation and instrumentation lines to perform a quantitative design analysis.

Please look at the following to learn more about FemtoJAVA pipeline [1], Sashimi Project [3] and CACO-PS [2] power estimation tool from Universidade Federal do Rio Grande do SUL (UFRGS), Brazil, head by Luigi Carro;

[1] CARRO, L. ; BECK FILHO, A C S . Low Power Java Processor for Embedded Applications. In: IFIP VLSI-SOC, 2003, Darmstadt. IFIP WG 105 Proceedings, 2003. p. 239-244.

[2] BECK FILHO, Antonio Carlos ; MATTOS, Julio ; WAGNER, Flavio ; CARRO, L. . CACO PS - A General Purpose Cycle-accurate Configurable Power Simulator. In: 16th Symposium on Integrated Circuits and Systems Design, 2003, São Paulo. Proceedings. Los Alamitos : IEEE Computer Society Press, 2003. v. 1. p. 349-354.

[3] ITO, S., CARRO, L., JACOBI, R. Sashimi and FemtoJava: making Java work for microcontroller applications. IEEE Design & Test of Computers. Estados Unidos: , p.100 - 110, 2001.

This circuit was originally generated on CACO-PS Format (FJA FILE) [2]. CACO-PS is A General Purpose Cycle-accurate Configurable Power Simulator written on C, from UFRGS, Brazil. A FJA file is a structural format. Each component on CACO-PS has a C function to describe its behavior. A parser to converter FJA on HDS was written by Alisson Garcia and Ricardo Ferreira. Each C behavior description was encapsulated on Java file to generate a HADES component. This implementation is based on a microprogram at FSM unit (File instruction.fji). Please wait until the applet is fully loaded. Then use the popup-menu ('edit') on the ROM component to open the window with preferences. The default (romadd.mif) its a simple program based on the following code: int a,b,c; a = 5; b = 7; c = a + b;

If you want to change the program, you can put these mif files in the box, then click on Load Mif file: romSortBubble.mif -> Bubble Sort Code romSortInsert.mif -> Sort Insert Code romSortQuick.mif -> Quick Sort Code romSortSelect.mif -> Select Sort Code

If you changed the default mif on the ROM, you will need to change the RAM component. Use the popup-menu ('edit') on the RAM component to open the window with the preferences.

ramSortBubble.mif -> If you choosed the Bubble Sort Code ramSortInsert.mif -> If you choosed the Sort Insert Code ramSortQuick.mif -> If you choosed the Quick Sort Code ramSortSelect.mif -> If you choosed the Select Sort Code

These mif(RAM and ROM) files are generated using Sashimi Tool. Now, you can start the simulation. If you want that the simulation runs automatic, just turn on the auto_clock, otherwise, you can control the clocks just clicking in manual_clock button.

The processor finish the default code in 90 cicles. Sort codes needs about 5800 cicles to finish.

The result can be found at the ram memory. For the default code, the result is placed at position 19. For the Sort codes, the vector generally start at position 20 (except for the ramQuickSort.mif).

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Impressum | 24.11.06