Hades logo    Hades applet banner

TAMS / Java / Hades / applets (print version): contents | previous | next

D*CORE memory subsystem demonstration

D*CORE memory subsystem demonstration screenshot


A demonstration of the D*CORE processor memory subsystem with RAM, ROM, and control registers. This applet is used in the context of the T3 laboratory course for interactive exploration of a typical microprocessor bus.

In the applet, interactive switches are provided to control the MAR (memory address register), the MDR (memory data register), and the MRR (memory read register). Note that flipflops are used in the write-enable and output-enable signals of the memories. This makes the timing slightly more complex, but is required in the real system to avoid memory corruption due to hazards on the control lines.

Use the switches to read a few words from the ROM, and try to write (and then read-back) a few words to the RAM. The microcode of the processor must later use the same sequence of control signals to read data from the bus, and to write data to the RAM.

For details, check the course material (in German) on our webserver.

Run the applet | Run the editor (via Webstart)

Impressum | 30.11.06