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D*CORE components and bus demonstration

D*CORE components and bus demonstration screenshot


A demonstration of several RTLIB components and the bus resolution function. This applet is used in the context of the T3 laboratory course to introduce the Hades simulator and basic RTLIB components.

Try to load all of the three different input values provided by the two IpinVector (top left and top center) and the Constant (top right) component into both Register components. Click the input switches to enable the corresponding three-state buffers that drive the bus, then enable the register and generate the required clock pulse(s). What happens if two (or all three) tri-state buffers are enabled at the same time?

For details, check the course material (in German) on our webserver.

Run the applet | Run the editor (via Webstart)

Impressum | 30.11.06