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Parallel Input/Output Adapter (Intel 8255)

Parallel Input/Output Adapter (Intel 8255) screenshot


This applet uses a fixed animation sequence to demonstrate the initialization and some basic input and output operations using the PIO 8255 or parallel input/output adapter. The PIO allows connecting a microcomputer system to a variety of external devices - with very few external components.

The whole animation runs for about eight minutes. See the previous applet for the description of the 8255 PIO chip and the fully interactive demonstration. For a typical microprocessor system using the 8255, click here.

FreeTTS Text-to-Speech Setup

This applet uses the FreeTTS text-to-speech system to generate spoken audio explanations during the animation. If the simulation and animation works when running the applet, but you can't hear the speech output, you have probably not yet changed the security settings of your browser's Java virtual machine. The speech synthesis in FreeTTS relies on a few operations (audio output, but also property accesses etc.) that are forbidden for untrusted applets. Therefore, to really run this applet with speech-output enabled, you might have to edit your Java security configuration file. The easiest way is to use our Java Policy Editor, which helps you to edit the security settings. Please visit the delaydemo with FreeTTS page for details.

8255 PIO description

The Intel 8255 chip integrates a standard (8-bit) microprocessor bus interface and 24 external signals, each of which can be programmed as an input or output line. The 24 external signals are organized into three groups of 8-bit each, called port A, port B, and port C. The bus-interface is asynchronous with the following behaviour:

  reset  nCS  nRD  nWR  A1  A0  data  |  behaviour
      1    *    *    *   *   *     *  |  device reset (mode 0, all inputs)
      0    1    *    *   *   *     *  |  device passive
      0    0    1    1   *   *     *  |  device selected
      0    0    0    1   A1 A0  read  |  read selected register or port
      0    0    1    0   A1 A0  write |  write selected register or port

      u    u    u    u   u   u     *  |  any undefined U,X,Z value will
                                      |  invalidate the simulation model

The chip contains four registers which are selected by two address inputs A1 and A0 during the read and write operations:

  A1 A0    
   0  0    port A data register
   0  1    port B data register
   1  0    port C data register
   1  1    control register

The 8-bit data written to the control register configures the 8255 and selects the operation mode, based on the following mapping:

    D7     1=mode selection 0=single-bit set/reset
    D6D5   groupA mode:  00=mode0 01=mode1 1*=mode2
    D4     portA:        0=output 1=input 
    D3     portC-upper:  0=output 1=input
    D2     groupB:       0=mode0  1=mode1
    D1     portB:        0=output 1=input
    D0     portC-lower:  0=output 1=input

The three modes are:

  Mode 0: for basic input and output operations,
  Mode 1: for unidirectional data-transfers with automatic handshake,
  Mode 2: for bidirectional data-transfers with handshake.

Please note that our simulation model only supports mode 0 at the moment. Any attempt to select mode 1 or mode 2 is ignored. Of course, you are welcome to write the additional logic yourself... Please let us know when you do so :-)

For example, writing the data word 0x80 (10000000) into the control register selects mode 0 for all ports and configures all ports as outputs. Afterwards, data written to one of the three data registers will appear immediately on the corresponding pins. On the other hand, writing the data word 0x9b (10011011) into the control register selects mode 0 and configures all ports as inputs. Subsequent read operations of the data registers will return the current input values at the corresponding pins. As a third example, the control word 0x89 (10001001) selects ports A and B as 8-bit outputs, the upper half of port C as a 4-bit output, and the lower half of port C as a 4-bit input. Subsequent writes to the port C data register will now drive the upper four bits of port C, while writing the lower four bits (configured as inputs) is ignored. Similarly, reading the port C data register will return the current four input values of the lower half of port C, merged with the upper four bits from the last port C write operation.

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Impressum | 24.11.06