The top row of components contains two subset (hades.models.rtlib.io.Subset) and one subset-and-flip (SubsetFlip) components. Use the property-sheet of those components to select the range of bits (upper and lower index) that should be extracted from the input signal. In the example, the first subset component extracts the lower four bits (3:0), while the second subset component extracts the upper four bits (7:4). While the subset-and-flip component is set to extract the lower four bits, it also reverses the bit pattern.
The remaining two components on the left side of the schematics are merge and merge-3 components. These take two and three multiple-bit input signals and construct a new, wider multiple-bit signal.
Unfortunately, the explicit bit-twiddling required in a schematics is (a lot) more cumbersome than the simple typing of subset-expressions in a text-based representation like VHDL source-code. It might be necessary to encapsulate complex bit-selection and -merging operations into their own subdesigns, in order to keep top-level schematics as clean as possible.
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