Synchronous counter (JK flipflops)

Description

A simple 4-bit synchronous counter built from JK-flipflops. In this circuit, the single clock signal is directly connected to all flipflops, so that all flipflops change state at the same time.

Click the clock and nreset input switches or type the 'c' and 'r' bindkeys to operate the counter.

An AND-gate with n inputs is used to drive the J and K inputs of the stage-n flipflop of the synchronous counter. This ensures that the flipflop only toggles if all lower-stage flipflops are 1. In other words,

Jn = Kn = Qn-1 AND Qn-2 AND ... AND Q1 AND Q0

Naturally, a cascade of AND-gates can be used to replace the multiple-input gates required for stages 4 and up.

Note that the synchronous counter requires more external logic that the asynchronous counter. Also, the AND gates that are used to calculate the carry signal(s) may slow down the maximum clock frequency of the synchronous counter.

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