Master-slave JK-flipflop (metastable)

Description

This circuit shows a typical master-slave JK-flipflop, built from two basic D-type NAND-latches. For a description of the normal circuit behaviour, read the documentation for the previous applet.

However, while the circuit in the previous applet was built from standard NAND gates, this applet uses special, metastable simulation models for the NAND gates. That means that the circuits look the same, and behaves the same under normal operation conditions. However, the behaviour for undefined input values or timing violations is completely different. While the metastable gates used in this circuit also accept all input values from the nine-valued std_logic logic model, they never generate an undefined (U or X) output value. Instead, they behave more or less like the real gates, which enter metastable states for a possibly long time before settling into one of the 0 or 1 output states. As a consequence of this gate behaviour, this circuit is much easier to initialize than the companion applet built from the normal gates. In fact, no extra reset input is required at all, because the flipflop gates will eventuall enter a (random) initial state. (Oscillations after timing violations are still possible, however).

Naturally, you might ask why Hades or the VHDL std_logic logic system don't use the metastable gates as the default, when the circuit initialization appears so much simpler with them. The obvious answer is that customers are usually not interested in how easy it is to design a circuit, but how well it works in practice. For example, the metastable gates used in this circuit will enter random states when encountering undefined inputs, so that multiple simulation runs with the same input values can result in different (and even random) simulation results. The point is that both the initialization problems and the circuit oscillations in the simulation indicate similar problems in the real circuit, which should be avoided. For example, problems to initialize a chip due to feedback problems and missing reset inputs can result in very hard-to-diagnose failures in the actual chips, ranging from complete malfunction to intermittent bugs. On the other hand, a digital circuit that is well-behaved in the simulation has a very good chance to work out-of-the-box after manufacturing.

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