CMOS: 6-transistor SRAM cell demonstration


	Informatics / TAMS / Applets / CMOS: 6-transistor SRAM cell demo \| basic CMOS gates

Description	The applet on this page demonstrates the typical six-transistor cell used for CMOS static random-access memories (SRAM). The cell consists of two cross-coupled CMOS inverters that store one bit of information, and two N-type transistors that connect the cell to the bitlines. To read the information, the wordline is activated while the external bitline drivers are switched off. Therefore, the inverters inside the SRAM cell drive the bitlines, whose value can be read-out by external logic (not shown in the applet). To write new data into the cell, the big (external) tristate drivers are activated to drive the bitlines. Next, the wordline transistors are enabled. Because the external drivers are much bigger than the small transistors used in the 6T SRAM cell, they easily override the previous state of the cross-coupled inverters. Still, a short-circuit condition arises (for a few nanoseconds) when changing the information.
6T-SRAM cell applet	To play with the applet, simply click the (left) mouse button on the three grayed areas on the left to toggle the input values for the corresponding input signal, namely data_in, wordline enable and write_enable. The applet then automatically updates the state of the SRAM cell. The colors are used to encode the logical values on the signal wires: red indicates VCC (e.g. +5 volts) blue indicates GND (ground, 0 volts) orange indicates a floating wire an open rectangle indicates a non-conducting MOS transistor Sorry, but your browser seems to ignore Java-applets. Enable Java in your browser preferences, and reload this page to start the SRAM-cell demonstration applet.
23.09.2008 Impressum	http://tams-www.informatik.uni-hamburg.de/applets/sram/index.html